1. Field of the Invention
The present invention relates in general to logic circuits, and, in particular, to an apparatus and method for resetting dynamic nodes in dynamic logic circuits.
2. Description of the Relevant Art
Logic circuits are the building blocks of microprocessors and are used to perform instructions and mathematical operations. Any instruction and mathematical operation may be implemented using a combination of logic gates. CMOS is often the preferred technology to implement such logic circuits.
There are two generally recognized methods of logic circuit design: static and dynamic. Dynamic logic circuits generally include devices in which signals decay over a period of time unless regenerated. CMOS random access memories are examples of this type of device. In contrast, devices which operate with essentially constant electrical conditions are considered static.
Shown in FIG. 1 is an example of a dynamic logic circuit 10 for implementing a logical AND operation on input signals IN.sub.0 and IN.sub.1. Logic circuit 10 includes a pair of N-channel field effect transistors (N-FETs) 12 and 14 connected in series between dynamic node 16 and ground, P-channel FET (P-FET) 20 connected between supply voltage V.sub.DD and dynamic node 16, inverter 22 connected between dynamic node 16 and output node 24, P-FET 26 connected between supply voltage V.sub.DD and dynamic node 16 and, N-FET 30 connected between dynamic node 16 and ground.
The gate electrodes of N-FETs 12 and 14 are configured to receive digital input signals IN.sub.0 and IN.sub.1. The gate electrode of P-FET 20 is configured to receive input RESET signal.
With continuing reference of FIG. 1 and with further reference to FIG. 4, the operational aspects of logic circuit 10 will now be described. At time t.sub.1, input signals IN.sub.0 and IN.sub.1 are asserted as high voltages (logical 1) thereby activating N-FETs 12 and 14. Presuming dynamic node 16 was previously charged to a predetermined high voltage, N-FETs 12 and 14 conduct current and discharge dynamic node 16 to a low voltage (logical 0). In response, inverter 22 generates at output node 24 a high voltage at time t.sub.2. Thus, the high voltage at output node 24 represents the logical AND of the high voltages at IN.sub.0 and IN.sub.1. P-FET 26 and N-FET 30 have their gate electrodes coupled to output 24 and operate to latch the voltages at dynamic node 16 and output node 24.
At time t.sub.4 RESET is asserted low thereby activating P-FET 20 to conduct current which recharges dynamic node 16 to its original predetermined high voltage. As shown in FIG. 4, RESET must be turned off at t.sub.5 (deassert to logic high) before subsequent input signals IN.sub.0 and IN.sub.1 are provided to N-FETS 12 and 14 in order to avoid a possible fault condition whereby dynamic node 16 is connected to both supply voltage VDD and ground via P-FET 20 and the combination of N-FETs 12 and 14, respectively.
The time between t.sub.1 and t.sub.5 is often referred to as the cycle time in dynamic logic circuits. To increase the speed at which dynamic logic circuits operate, designers seek to reduce cycle time by reducing RESET time. There is a limit to the reduction of RESET since RESET must be made wide enough to ensure dynamic node 16 is precharged properly under all scenarios which take into account the process skew, RESET slew rate, RESET collision current etc. Extensive analysis must be employed to determine the precise RESET pulse to be provided to dynamic logic circuits in order to satisfy, as much as possible, all competing factors. Typically, marginal time is added to the width of RESET to ensure the dynamic node is properly precharged. Calculating and implementing precise pulses to dynamic circuits such as RESET, is known to be difficult and costly in modern logic circuit design.